In recent years, with improvement in function and performance of semiconductor devices, patterns have been reduced in size to integrate as many semiconductor elements as possible. However, the degree to which the number of semiconductor elements to be mounted on a semiconductor substrate increases is much higher than the degree to which patterns are reduced in size. Thus, there has been a need for increasing the area of such a semiconductor substrate. For example, as the performance of an imaging apparatus increases, the size of an imaging element increases. Thus, there has been a need for semiconductor devices with a large frame size called 35 mm full frame.
In general, photolithography is used for manufacturing semiconductor devices. The photolithography is a technology for obtaining a desired pattern by applying a resist on a semiconductor substrate, exposing the resist through a mask having a pattern using an exposure machine, and then developing the resist. However, the pattern of an element required for the large semiconductor device as described above may have an area that is larger than the area that can be exposed by the exposure machine. For example, an imaging section of a 35 mm full-frame semiconductor device described above alone has a size of 36 mm×24 mm. Because the size of a peripheral circuit section is also added, the size of the entire semiconductor device will further increase. However, for example, the area that can be exposed by a general exposure machine is about 33 mm×26 mm. Thus, a pattern cannot be formed by a single exposure.
Thus, to form such a large semiconductor device, stitching exposure is used. In the stitching exposure, a semiconductor device is divided into a plurality of regions of exposable size, and the regions are separately exposed and stitched together.
As an example, FIG. 17 illustrates a solid-state imaging device 11 that includes an imaging section 12 and a peripheral circuit section 13, and that is separated by a scribe region 14. The pattern of the solid-state imaging device 11 has an area larger than an area that can be exposed at once. Thus, the pattern is divided, at a dividing position (a stitch 15), into two divided patterns 16a and 16b, which are separately exposed to provide a desired pattern.
In the stitching exposure described above, importance is placed on high stitching accuracy with which the divided patterns 16a and 16b are stitched. When the stitching accuracy is not high enough, a failure such as a circuit disconnection occurs at the stitch 15.
To improve the stitching accuracy, overlay inspection marks, alignment marks, and other marks may be formed using a single mask, and the pattern of a semiconductor element divided into a plurality of regions reflected by respective masks may be exposed while these regions are each aligned with an associated one of these marks (see Japanese Patent No. 5062992 (Patent Document 1)). Such a method can eliminate displacements of a pattern positioned on the mask, and displacements of a mask positioned on the mask stage of the exposure machine, thus improving stitching accuracy.